AveCEC supports the entire design process and can be implemented independently of any tool and can handle large designs. More than half of the designs require re-spin. The main reason for re-spin is functional error; AveCEC uses mathematical methods to exhaust all situations without using test vectors to ensure that the design implementation is consistent with the gold design.

AveCEC has the following features and advantages:

1.Tools are fast and more efficient than simulations, and they are not an order of magnitude.

2.Quick troubleshooting, strong ability to debug.

3.Complex datapath optimization.

4.Support advanced door clock design optimization (Clock Gating).

5.Scalability: Verification of the entire SOC design.

6.Support FPGA design flow.